VLSI Design using VHDL Training

[tabs type=”horizontal”]
[tab title=”Course Content”] Trainingds Summer Training Program on VLSI Design with VHDL is a 6 weeks training program in the fields of VHDL Basics, Combinational Circuits, Sequential Circuits and Advanced Circuits. This training program mainly designed for students of B.Tech, B.E. This vocational training course in VLSI design using VHDL will give you a chance to learn VLSI using tools like MODELSIM, XILINX.

VHDL is an acronym for VHSIC Hardware Description language (VHSIC stands for Very High Speed Integrated Circuits). It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system, or anything in between.

Who is this training for:

  • Students from second years onwards of BE / B. Tech. courses (Electronics, Electronics & Telecommunication, Instrumentation, Electrical, Computer Science, IT, Chemical).

Place: Inhouse
Duration: 6 Weeks (2 hours/Day)
Organization of content: 60% Lecture, 40% Lab

There will be separate lab sessions on same days:
Tools:MODELSIM 6.5se & Xilinx 13.0 ISE

[tab title=”Syllabus”]
[accordion title=”VLSI”]

  • Introduction to VLSI
  • Learning objectives
  • Flow of ASIC
  • PLD Types
  • CPLD
  • FPGA
  • FPGA Flow
  • System On Chip


[accordion title=”VHDL”]

  • Introduction to HDL
  • VHDL
  • Data types
  • Constants and Variables
  • Operators
  • Built-in Functions
  • Different Modeling style  of VHDL
  • Dataflow coding style
  • Behavioral coding style
  • Structural coding style
  • Mixed coding style
  • RTL coding
  • Entity
  • Architecture
  • Process
  • Signals & Concurrency
  • User defined Data types
  • VHDL programming
  • Process
  • Sensitivity List
  •  If then else
  • Case Statement
  • Branches and control structure
  • loop statement
  • for loop
  • while loop
  • Wait  statement
  • Concurrent VHDL
  • With Select
  • Generate Statement
  • For Generate
  • If Generte
  • Test Bench
  • Types of Test Bench
  • Function
  • Packages
  • Attributes
  • Delays in VHDL

[accordion title=”LAB-ASSIGNMENT”]

  • Introduction to Modelsim EDA
  • Lab assignments
  • Lab assignments
  • Introduction of Xilinx EDA
  • FPGA Board Interface
  • Chip Programming
  • Project Guidance
  • Test
  • Result
  • Feed back

[tab title=”Apply Online”]
[contact-form-7 id=”845″ title=”Online_Application”]

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